高速视频处理系统中的信号完整性分析 摘要：结合高速DSP图像处理系统讨论了高速数字电路中的信号完整性问题，分析了系统中信号反射、串扰、地弹等现象破坏信号完整性的原因，通过先进IS工具的辅助设计，找出了确保系统信号完整性的具体方法。 关键词：高速电路设计 信号完整性 DSP系统 深亚微米工艺在IC设计中的使用使得芯片的集成规模更大、体积越来越小、引脚数越来越多；由于近年来IC工艺的发展，使得其速度越来越高。从而，使得信号完整性问题引起电子设计者广泛关注。 在视频处理系统中，多维并行输入输出信号的频率一般都在百兆赫兹以上，而且对时序的要求也非常严格。本文以DSP图像处理系统为背景，对信号完整性进行准确的理论分析，对信号完整性涉及的典型问题[1]——不确定状态、传输线效应、反射、串扰、地弹等进行深入研究，并且从实际系统入手，利用IS仿真软件寻找有效的途径，解决系统的信号完整性问题。 1 系统简介 为了提高算法效率，实时处理图像信息，本图像处理系统是基于DSP+FPGA结构设计的。系统由SAA7111A视频解码器、TI公司的TMS320C6701 DSP、Altera公司的EPlK50QC208 FPGA、PCI9054 PCI接口控制器以及SBRAM、SDRAM、FIFO、FLASH等构成。FPGA是整个系统的时序控制中心和数据交换的桥梁，而且能够对图像数据实现快速底层处理。DSP是整个系统实时处理高级算法的核心器件。系统结构框图如图1所示。 在整个系统中，PCB电路板的面积仅为15cm×l5cm，系统时钟频率高达167MHz，时钟沿时间为0．6ns。由于系统具有快斜率瞬变和极高的工作频率以及很大的电路密度，使得如何处理高速信号问题成为一个制约设计成功的关键因素。 2 系统中信号完整性问题及解决方案 2．1 信号完整性问题产生机理 信号的完整性是指信号通过物理电路传输后，信号接收端看到的波形与信号发送端发送的波形在容许的误差范围内保持一致，并且空间邻近的传输信号间的相互影响也在容许的范围之内。因此，信号完整性分析的主要目标是保证高速数字信号可靠的传输。实际信号总是存在电压的波动，如图2所示。在A、B两点由于过冲和振铃[2]的存在使信号振幅落入阴影部分的不确定区，可能会导致错误的逻辑电平发生。总线信号传输的情况更加复杂，任何一个信号发生相位上的超前或滞后都可能使总线上数据出错，如图3所示。图中，CLK为时钟信号，D0、D1、D2、D3是数据总线上的信号，系统允许信号最大的建立时间[1]为△t。在正常情况下，D0、D1、D2、D3信号建立时间△t1<△t，在△t时刻之后数据总线的数据已稳定，系统可以从总线上采样到正确的数据，如图3(a)所示。相反，当信号D1、D2、D3受过冲和振铃等信号完整问题干扰时，总线信号就发生了相位偏移和失真现象，使D0、D1、D2、D3信号建立时间△t2>△t，系统在△t时刻将从总线上得到错误数据信息，产生错误的控制信号，扰乱了正常工作，使信号完整性问题更加复杂，如图3(b)所示。 2．2 信号的反射 信号的反射就是指在传输线端点上有回波。当传输线上的阻抗不连续时，就会导致信号反射的发生。在这里，以图4所示的理想传输线模型来分析与信号反射有关的重要参数。图中，理想传输线L被内阻为Ro的数字信号驱动源Vs驱动，传输线的特性阻抗为Zo，负载阻抗为RL。在临界阻抗情况下，Ro＝Zo=RL，传输线的阻抗是连续的，不会发生任何反射。在实际系统中由于临界阻尼情况很难满足，所以最可靠的适用方式是轻微的过阻尼，因为这种情况没有能量反射回源端。 负载端阻抗与传输线阻抗不匹配会在负载端(B点)反射一部分信号回源端(A点)，反射电压信号的幅值由负载反射系数几决定，可由下式求出： PL=(RL-Z0)/(RL+Z0) (1) 式中，PL称为负载电压反射系数，它实际上是反射电压与入射电压之比。由式(1)可知—1≤PL≤+1，当RL=Zo时，PL＝0，不会发生反射。可见，只要根据传输线的特性阻抗进行终端匹配，就能消除反射。从原理上说，反射波的幅度可以大到入射电压的幅度，极性可正可负。当RLZo时，PL>0，处于欠阻尼状态，反射波极性为正。当从负载端反射回的电压到达源端时，又将再次反射回负载端，形成二次反射波，此时反射电压的幅值由源反射系数PS决定，可由下式求出： Ps=(R0-Zo)/(R0+Z0) (2) 在高速数字系统中，传输线的长度符合下式时应使用端接技术： L>tr/(2tpdl) (3) 式中，L为传输线线长，tr为源端信号的上升时间，tpdL为传输线上每单位长度的带载传输延迟。即当tr小于2TD(TD为传输延时)时，源端完整的电平转移将发生在从传输线的接收端反射回源端的反射波到达源端之前，这需要使用端接匹配技术，否则会在传输线上引起振铃。 结合图1设计本系统时，采用MentorGraphics公司的信号完整性分析工具InterconnectSynthesis(IS)，信号驱动器和接收器均使用TTL_S工艺器件的IBIS模型进行电路仿真，选择出正确的布线策略和端接方式。DSP与SBSRAM接口的时钟高达167MHz，时钟传输和延时极小，很容易在信号线出现反射现象。根据公式(2)，要消除源端的反射波必须在源端进行阻抗匹配，使反射系数PS为0。用interconnectSynthsis仿真测试可得此时钟线的传输阻抗Zo=47Ω。因此，在DSP的SDCLK时钟的输出端应采用串联匹配法[1][3]，串入47Ω的电阻进行源端匹配消除源端的信号反射现象。对于负载端的反射，根据公式(1)，要使PL＝0，必须保证负载阻抗RL＝Zo。因此，在SBSRAM的时钟输入端口应采用戴维南终端匹配法[1][3]，并联两个电阻R1和R2且R1＝R2=94Ω(R1//R2＝Zo)实现终端匹配，其端接前后InterconnectSynthesis仿真的波形如图5所示。端接后信号线的反射噪声明显减小，满足了系统对时钟信号完整性的要求。 2．3 信号的串扰 串扰是指当信号在传输线上传播时，因电磁耦合对相邻传输线产生不期望的电压或电流噪声干扰。随着电子产品的小型化，PCB板线间距减小，串扰问题更加严重。 对于高速电路来说，一般都采用平板电源地层，两导体间的串扰取决于它们的耦合电感和耦合电容[3]。在数字电路设计中，通常感性串扰要比容性串扰大，所以应重点考虑导线间的互感问题。两导体间的感性串扰系数计算可以通过下式得出： 式中，常数k取决于信号的建立时间和信号线的干扰长度(平行长度)；H为信号线到平板地层的距离；D为两干扰线的中心的距离。由(4)式可知，串扰大小与线间距(D)成反比，与线平行长度(K)成正比，与信号线距地层的距离(H)成正比。针对这些串扰的特性，结合图1设计本系统时，主要用以下几种方法减少串扰：(1)加大线的间距，尽可能减少DSP与SBSRAM、SDRAM以及FPGA之间高速信号线的平行长度，必要时采用jog方式走线；(2)高速信号线在满足条件的情况下，加入端接匹配减少或消除反射，从而减小串扰；(3)将信号层的走线高度限制在高于地平面10mil左右，可以显著减少串扰；(4)用InterconnectSynthsis进行仿真时，在串扰严重的两条线之间插入一条地线，可以起到隔离作用，从而减少串扰。 2．4 地弹噪声 随着数字设备的速度变快，它们的输出开关时间越来越少。当大量的开关电路同时由逻辑高变为逻辑低时，由于地线通过电流的能力不够，电流涌动就会引起地参考电压发生波动，称之为地弹。 在地弹现象的分析中，对驱动设备来说，外部设备都被看作容性负载即(Cl～Cn)。这些容性负载储存的电荷量Q可由下式决定： Q＝V×C 上式中，V是电容器两端上的电压，C是容性负载的电容。 一个设备外界和地线通路都有内在的电感L[2]。在大量数字逻辑输出由高电压变为低电压的过程中，储存在负载电容的电荷会涌向设备地，这个电流浪涌会通过电感L产生电压V GND，其大小可用下式得出： VGND=L×(di/dt) 由于系统地和设备地之间的电压VGND的存在，对于各逻辑器件来说，其有效输入电压值为：VACTIVE＝VIN—VGND。如果地弹产生的电压值VGND过大，就会导致各器件对输入电压判断的错误，扰乱整个系统的正常工作。 结合图1设计本系统时，由于FPGA控制逻辑部分存在大量快速开关输出电路，当这些开关电路同时发生逻辑变化时，产生的开关电流会涌入地平面回路，破坏地平面的参考电压，引入地弹噪声。对于地弹噪声的干扰，通过下面几种方法可减小地弹对电路的影响：(1)增加VCC／GND间的去耦电容个数，并尽可能使其与Vcc／GND对数相等；(2)降低器件的输出容性负载，减少负载器件个数；用SN74LVTH62245驱动器实现FPGA同步输出引脚与DSP数据线的隔离；用SN74LBI6244构成地址隔离，降低同步噪声对DSP高速电路的干扰；(3)在电源输入端跨接10～100μF的电解电容，在每个集成电路芯片都布置一个O．1μF的瓷片电容，滤掉电源和地的噪声信号；(4)对于抗噪能力弱、关断时电源变化大的SBSRAM、SDRAM存储器件，在芯片的电源线和地线之间接入0．1μF的退耦电容。在采取地弹噪声处理后利用频谱分析仪测得系统的骚扰频谱，可以发现频谱已经变得很平坦，骚扰电平已降到系统容许的范围以内，达到了系统对地参考电压的要求。 在高速电路设计中，信号完整性问题是一个复杂的问题，往往有许多难以预料的因素影响整个系统的性能。因此信号完整性分析在高速电路设计中的作用举足轻重，只有解决好高速设计中的信号完整性问题，高速系统才能准确、稳定地工作。 High-speed video processing system of signal integrity analysis Abstract: combining the high-speed DSP image processing system, discusses the high-speed digital circuit, signal integrity, analyzes the problems in the system of signal reflections, ground, such phenomena as the signal integrity, destroyed by advanced design, the auxiliary tool IS found to ensure the integrity of the specific method of signal system. Commercial advertisements The latest TL082CDT: AT45DB041 sells chip MC74HC04AD SII141BCT80 HD6417707RF60 RC - AD9280ARS CXA1081M CXA1635M PI5C16861A STLC5412FN Keywords: high-speed circuit design signal integrity DSP system Deep submicron process in IC design makes the use of chip integrated larger, more and more small volume, pin number more, Due to the recent development of IC technology, make its speed is getting higher and higher. Thus, makes the signal integrity problems caused extensive concern of electronic designers. In video processing system, input and output signal of multidimensional parallel commonly in frequency over 100 MHZ of timing requirements, but also very strictly. Based on DSP image processing system for signal integrity as the background, theoretical analysis, the accurate signal integrity of typical problems involved in [1], uncertainty, transmission and reflection, the effect of ground, etc, and in-depth study from actual system by simulation software, IS looking for effective ways to solve the system, signal integrity problem. 1 system In order to improve the efficiency of the algorithm, the real-time image information, the image processing system is based on DSP + FPGA design. Video codecs, SAA7111A system consists of TI company TMS320C6701 DSP, Altera company EPlK50QC208 FPGA, PCI9054 PCI interface controller and SBRAM, SDRAM, FIFO, FLASH, etc. The whole system is the FPGA sequential control center and data exchange, and able to bridge of image data quickly. DSP is the system of the core real-time senior algorithm. System structure diagram is shown in figure 1. In the system, PCB for 15cm l5cm x only, the system clock frequency clock time, as 167MHz along ns. Due to the system has the high slope fast transient and the working frequency and great circuit, how to deal with high density restriction design problem becomes a signal is the key factor to success. 2 system signal integrity problems and solutions signal integrity problem generating mechanism Signal integrity refers to the signal transmission through physical circuit, signal waveform and the receiver to see the sender sends signal waveform in error range, and spatial adjacent signals interactions are permitted scope. Therefore, the signal integrity analysis of the main target is the reliable guarantee high speed digital signal transmission. Actual signal voltage fluctuation, there is always shown in figure 2. In A and B two due to overshoot and ringing [2] to signal amplitude into the shaded part of uncertainty, may cause errors logic level. Bus signal transmission of the situation is more complex, any signal on the phase lag could advance or data error on the bus, as shown in figure 3 below. In the diagram, as the clock signal, D0 CLK, D1, D2, D3 is the data bus signals, systems allow the maximum signal established time [1] for the train. In normal circumstances, D0, D1, D2, build time signal D3 t1 < train and train in the train t moments after the data stability data bus, the system can from the bus to the correct data sampling, as shown in figure 3 (a). Conversely, when the signal D1, D2, educated and ringing D3 signal integrity, bus signal interference problems occurred in phase offset and distortion, make D0, D1, D2, build time train t2 D3 signal system in > train t t will train from the bus get error data, the control signal, disturbed the normal work, make the signal integrity problem is more complex, as shown in figure 3 (b). The reflected signals The reflected signals in line with echo endpoint. When the transmission line impedance discontinuity, will cause the signal reflections. Here, in the ideal 4 transmission model to analysis and reflection signals about the important parameters. In the figure, the ideal transmission by resistance for the Ro L digital signal source driver drive, the transmission Vs the characteristic impedance Zo, load impedance for for RL. In critical impedance Zo circumstance, Ro = = RL, transmission impedance is continuous, won't produce any reflection. In the actual system can not meet the conditions due to critical damping, so the most reliable applicable way is slightly over damping, because this is not the source of energy reflected back. The load impedance and transmission impedance mismatch in the load (B) of the source signal reflected back (points), reflected voltage signal amplitude of reflection coefficient of load, under A decision by A type: PL = (RL - Z0) / (RL + Z0) (1) Type, PL called load voltage reflection coefficient, it is actually reflected voltage and the incidence of voltage. By type (1) known - 1 + 1, than PL acuities when RL = Zo, PL = 0, won't happen. Visible, according to the characteristics of transmission impedance terminal matching, we can eliminate reflected. From the theory of reflection wave amplitude, said to the incident voltage can be, which negative polarities. When RL < < 0 Zo, PL, in the state of damping, had reflected wave polarity is negative, When RL > > 0 Zo, PL, in the state of reflection wave damping, for polarity. When the load reflected back from the client to the source voltage, and will again reflected back to load, formed secondary reflected wave, reflected voltage amplitude of the source of reflection coefficient decided by the next, PS of a type: Ps = (R0 - Zo) / (R0 + Z0) (2) In high speed digital systems, the length of the transmission line should be used when the next type with technology: L > tr / (2tpdl) (3) Type, L for transmission/long tr is the source, the rise time of signal transmission line, tpdL per unit length for carrying the belt transmission delay. When 2TD < tr (TD for transmission delay), the complete source of multilevel transfer will occur in the transmission from the source end receiver reflected back to the reflection wave source, the need to use before termination matching technology, otherwise it will cause ringing in the transmission line. Combined with the system design of figure 1, MentorGraphics using the signal integrity analysis tools Co., InterconnectSynthesis (IS), signal receiver using drivers and TTL_S craft device IBIS model simulation, choose the correct wiring strategy and termination methods. DSP and SBSRAM interface as the clock 167MHz, clock and delay in tiny, easily reflected signal. According to the formula (2), to eliminate the reflected wave source in the source end must be on impedance matching, make the reflection coefficients for 0. PS. With interconnectSynthsis simulation test can the clock line transmission impedance Zo = 47 Ω. Therefore, in SDCLK DSP clock output should adopt series matching method [1], [3], string into Ω 47 on the resistance of the signal source to eliminate reflected. According to the reflection, load formula (1), to make PL = 0, must guarantee load impedance Zo RL =. Therefore, in SBSRAM clock input should adopt the terminal matching method [1], [3], parallel two resistance R1 and R2 and R1 = R2 = 94 Ω (R1 / / R2 = Zo), JiDuan before termination matches up InterconnectSynthesis simulation of the waveform as shown in figure 5. After the termination of the reflected signal noise, to meet the system clock signal integrity. The signal of Crosstalk refers to spread in line when signal by electromagnetic coupling, adjacent to produce unexpected transmission line voltage or current noise interference. As the miniaturization of electronic products, PCB line spacing, crosstalk problem is more serious. For high-speed circuits, usually by power between the two conductors formation, depending on their cross coupling capacitance and inductance coupling [3]. In the digital circuit design, usually perceptual link to hematocrit of sex, so shall consider the mutual inductance between the wires. Between two conductors of calculating coefficients of sensibility next type that can be through: Type, constant k depends on the establishment of the signal and the disturbance signal length (parallel length), H for signal to the distance; flat strata, D for two interference lines of center distance. By (4) type, size and cross line spacing (D), and inversely proportional to parallel length (K) is proportional to the distance from the strata signal proportional to the (H). According to these characteristics, the combination of the system design of figure 1, mainly in the following methods of reducing (1) increasing line spacing, minimize DSP and SBSRAM, SDRAM between signal and FPGA, high-speed parallel length by jog means necessary wiring, (2) high signal on the circumstances, join termination matches to reduce or eliminate reflected, thus reduce crosstalk, (3) will signal lines layer above ground height in 10mil around, can significantly reduce crosstalk, (4) InterconnectSynthsis using simulation, the serious in crosstalk between two lines, can rise to insert wire isolation effects, thereby reducing the crosstalk. ground noise Along with the digital equipment faster, their output switch with less and less time. When a switch circuit by logic high into a logical low, because of the ground through the current capacity, the current surge will not happen to a reference voltage fluctuation caused, call to play. In the analysis, the phenomenon of elastic to drive equipment, external devices are regarded as capacitive loads namely (Cl ~ Cn). The capacitive loads can be stored charge quantity Q: by next type Q = V x C The type of capacitor, V is in the voltage, C are capacitive loads of capacitance. A device outside and ground pathways are inherent inductance L [2]. In large Numbers of high voltage output logic to low voltage, the process of load capacitance stored in charge will be flocking to the electric equipment, stray inductance L produced by surge voltage GND V, its size, type used under VGND = L x (di/dt) Due to the system and equipment to the voltage between VGND, for each logical device, the effective input voltage values for VACTIVE = VIN - VGND:. If the voltage produced to play VGND too, can cause various components of the input voltage error of judgment and disrupt the normal work of the whole system. Combined with the system design of figure 1, because the FPGA control logic part a quick switch output circuit, when the switch logic circuit occur at the same time, the switch currents generated into the ground plane loop, will destroy the ground plane, introduction to play a reference voltage noise. To play for the noise, through the following method can reduce the influence of the circuit to play: (1) the increase of the VCC/GND decoupling capacitor, and as far as possible the number with the VCC/GND logarithmic equal, (2) reduce the output devices, reduce the capacitive loads load device number, SN74LVTH62245 drive with FPGA realizing synchronization output pin data with DSP isolation, With SN74LBI6244 constitute the address, lower noise high-speed circuits of DSP synchronization of interference, (3) in the power input jumper 10 ~ 100 mu F the electrolytic capacitor, in every integrated circuit chips are decorated a o. 1 F ceramic capacitors, close to filter out the noise signal and power, (4) for antinoise ability weak, shut off the power supply when the big change, SDRAM storage devices, SBSRAM in chip power and ground between muon F of access decoupling capacitors. In the ground to handle by spectrum analyzer after noise measurement system of harassment can be found, frequency spectrum has become very smooth, harassing level has dropped for system within the reach of voltage reference system. In high-speed circuit design, the signal integrity problem is a complex problem, often have many uncertain factors affect the performance of the system. Therefore signal integrity analysis in high-speed circuit design, the only solution plays an important role in the design of high-speed signal integrity, high-speed system can accurately, steady job.
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